Ferroelectric random access memory elements (FERRAMs) for integrated circuits take advantage of the properties of a ferroelectric dielectric material as a capacitor dielectric. Preferred ferroelectric dielectric materials are those of a perovskite structure, including titanates such as lead zirconate titanate (PZT), barium strontium titanate, and many others. Typically these ferroelectric dielectric materials have a very high dielectric constant (.epsilon.&gt;&gt;100) compared with conventional capacitor dielectrics used in integrated circuits, e.g. SiO.sub.2 and Si.sub.3 N.sub.4 (.epsilon.&lt;10). Moreover, one of two stable polarization states may be induced in a ferroelectric material, dependent on the polarity of an applied voltage, and the ferroelectric material remains in a selected polarization state after removal of the voltage. Thus a high density ferroelectric memory element may be provided which is non-volatile. Other known advantages of FERRAMs are that they are programable with less than 5 V, have fast access times (&lt;40 ns), consume low power, are robust with respect to a large number of read/write cycles, and exhibit radiation hardness.
The interest in using ferroelectric materials for applications for non-volatile DRAMs has led to rapid development of improved processes for deposition of layers of ferroelectric dielectric materials. Known deposition methods which have been investigated for integrated circuit applications include, for example, metallo-organic sol-gel and other spin-on liquid processes, chemical vapour deposition (CVD), sputtering, laser ablation, electron beam deposition and ion beam deposition.
On the other hand, integration of ferroelectric capacitors into complementary metal oxide semiconductor (CMOS), bipolar, or bipolar-CMOS integrated circuits requires a process which is compatible with known process technology.
As an example, in a known conventional DRAM memory cell of one capacitor/one transistor type having charge stored in a memory cell capacitor, the capacitor is selectively coupled through the source-drain path of a MOS field effect transistor (access transistor) to a bit line, and the gate electrode of the access transistor is coupled to a word line. A conventional approach to building memory cells involves formation of access transistors in a semiconductor substrate wafer and fabrication of a planar capacitor structure on top of a dielectric layer, e.g. a field isolation layer, on the substrate adjacent to each transistor. Capacitors are formed conventionally by deposition of a first conductive layer, a capacitor dielectric layer and an overlying second conductive layer. The sandwich of layers is patterned and etched to define each capacitor, i.e. first and second conductive electrodes and an intervening capacitor dielectric.
Etching is typically accomplished by a dry etch process, e.g. reactive ion etching. However, problems arise in applying conventional dry etch chemistry for patterning ferroelectric dielectric materials such as PZT (PbZr.sub.x Ti.sub.1-x O.sub.3) which include elements not found in conventional semiconductor materials.
A publication by Sanchez et al. for the International Symposium on Integrated Ferroelectrics, 1991, entitled "Process technology developments for GaAs ferroelectric non-volatile memories" describes the use of a step of ion milling to etch and define a top electrode and an underlying ferroelectric dielectric layer, followed by masking and another step of ion milling to define the lower electrode.
Alternatively, wet etching methods for patterning ferroelectric materials have been investigated for fabrication of conventional flat plate capacitors with a ferroelectric dielectric material, for example as described in U.S. Pat. No. 4,759,823 to Asselanis, entitled "Method for Patterning PLZT thin films".
Furthermore, many perovskite ferroelectric dielectrics of interest for FERRAMs react with silicon and silicon containing materials. Thus, a conventional DRAM cell structure having polysilicon electrodes, or a bottom electrode provided by a region of a silicon substrate, is not feasible.
Ferroelectric dielectric materials are also known to react and interdiffuse with conventional dielectric materials, e.g. silicon dioxide, silicon nitride. Interdiffusion of impurities may occur at the interface between a ferroelectric capacitor dielectric and a conventional dielectric. Other interactions of ferroelectric materials occur with conductive layers used for electrodes. The latter, for example, can result in formation of non-conductive oxides at the electrode interface.
Diffusion of elements such as lead and titanium, and reaction of the ferroelectric material with electrode materials with which they are in contact may be avoided by provision of a suitable barrier layer between the ferroelectric material and the electrode material. Alternatively an appropriate electrode material must be selected which does not significantly interdiffuse or react with the ferroelectric material.
For example, processes are described for formation of ferroelectric capacitors based on a conventional thin capacitor cell structure, using multilayer electrodes in U.S. Pat. No. 5,122,477 to Wolters et al. (Philips) entitled "Method of manufacturing a semiconductor device comprising capacitors which form memory elements and comprise a ferroelectric dielectric material having multilayer lower and upper electrodes". Selected metal and metal oxide electrode materials for thin film capacitors with ferroelectric dielectrics are described in U.S. Pat. No. 5,122,923, to Matsubara (NEC) entitled "Thin film capacitors and process for manufacturing the same". Other thin film ferroelectric capacitor structures are described in U.S. Pat. No. 5,109,357 to Eaton, Jr. (Ramtron) entitled "DRAM memory cell and method for operation thereof for transferring increased amount of charge to a bit line" and U.S. Pat. No. 5,187,638 to Sandhu (Micron Technology) entitled "Barrier layers for ferroelectric and PZT dielectric on silicon".
However, it is desirable for bipolar CMOS integrated circuits that a process for forming a ferroelectric capacitor should be compatible with conventional known silicon process technology, so that ferroelectric elements may be fully integrated with bipolar and CMOS integrated circuit devices with a minimum number of additional mask levels, and without unduly adding to the overall number of process steps and process complexity.